Image sensors often use high-speed A/D converters. These converters must strike a balance between speed and power consumption. Faster converters will allow faster image acquisition. However, these often consume much more power than other, slower, converters.
A successive approximation A/D converter may represent a good trade-off between speed and power consumption. It has been suggested to use multiple successive approximation A/D converters in a pipeline type architecture. The conversion of the multiple pixels is thus pipelined, thereby increasing the overall conversion speed, while maintaining the advantageous power consumption characteristics of the successive approximation converter.
Generation of multiple timing and control signals for such a pipelined system may be complicated.
The present application teaches a new architecture which enables high speed A/D conversion, with multiple successive approximation cells in the conversion system.
According to an embodiment, groups of sample and hold circuits, and groups of A/D converters are controlled using a clocking scheme.